1. Technical Field
The present invention relates to a voltage regulator, and more particularly to a voltage regulator for semiconductor memories such as dynamic random access memory (DRAM).
2. Description of Related Art
Along with the rapid development of science and technology at the present, semiconductor memories, as major storage devices for large amount of data are being developed to have larger and larger capacity. As the semiconductor technology is continuously scaled down to achieve high memory density, on-chip voltage regulators providing lower supply voltage for internal circuits are required to fulfill the requirements for device reliability and low power consumption. For DRAM, the bit line sensing, restoring operation in the memory cell arrays consume current abruptly and heavily. For high density DRAM chip, it is challenging to design on-chip voltage regulators for memory cell arrays providing a stable voltage level (such as VCCSA) with sufficient and appropriate supplying current.
The bit line sense amplifier will be activated when the bit line signal is large enough. The latch nodes connected to the bit line (BL) and the bit line bar (BLB) of the memory cell are sensing to the voltage signals VCCSA and VSS, such that the memory cell can be restored to the voltage signal VCCSA or VSS. However, during sensing, the voltage signal VCCSA will be dropped since the voltage signal VCCSA is used to charges up the bit line or the bit line bar from the plate voltage VCP to the voltage signal VCCSA. If the voltage signal VCCSA drops too low, the sense amplifier will have a stable issue, and thus the data will flip.
An over-drive (or kick) design is used to supply the voltage signal VCCSA besides from the sensing amplifier, and avoid the data flip. Unfortunately, the over-drive design may provide the too strong or weak voltage signal VCCSA since the voltage signal VCCSA comes from an external power VDD having a variation from the maximum and minimum levels of the external power VDD. In circuit design, there is larger margin to cover, and the external power VDD will be larger than the maximum level and lower than the minimum level of the external power VDD. Therefore, the duration to provide the over-drive also affects the voltage signal VCCSA.